74AS00 Quad 2-Input NAND Gate. Physical Dimensions inches (millimeters) unless otherwise noted (Continued). Lead Plastic Dual-In-Line Package ( PDIP). 74AS00 Datasheet, 74AS00 PDF, 74AS00 Data sheet, 74AS00 manual, 74AS00 pdf, 74AS00, datenblatt, Electronics 74AS00, alldatasheet, free, datasheet. description. These devices contain four independent 2-input positive-NAND gates. They perform the Boolean functions Y = A • B or Y = A + B in positive logic.

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Where would you use the latter instead of the former? Use a 1K potentiometer to supply a variable input voltage. The propagation delay inherent in gates can be useful for creating oscillatory circuits. In order to put into 74a00 where the above devices fit into the scheme of things and how far we have come, it would be instructive to look at a chronology of computer electronics. Observe here that the circuit elements associated with Q4 in the totem-pole circuit are missing and the collector of Q3 is left open-circuited, hence the vatasheet open-collector.

What happens when the outputs of two totem-pole outputs are connected together? Analyze the circuits and explain the results. Measure the voltage present at the input pin when no connection is made to it. What is the lowest value of Datashheet such that the output is still HI?

What is the smallest value of R such that the output is still LO?

Complex electronic circuits for high volume production are produced today using ASICs application specific ICs datasheett entirely using a computer-aided design CAD system. These two tend to be directly related, i. Digital IC manufacturers are continually trying to minimize the delay-power product and continue to produce families with different characteristics to suit specific needs.

Calculate the range of values for this resistor. Problem 8 – Timer The timer Fatasheet is a popular circuit for generating asymmetric rectangular waves. Another common structure is CMOS complementary metal-oxide-silicon technology which exhibits low power and high noise immunity.

The voltage at the output pin is indeterminate and is said to be floating.

Problem 7 – Schmitt trigger oscillator Construct this simple oscillator and measure the frequency of oscillation for a given R and C. Conversely, when Q3 is open, Q4 is closed.

Problem 10 What is meant by negative logic? Measure both the input voltage and the logic output of the inverter.

### (PDF) 74AS00 Datasheet PDF Download – Quadruple 2-Input Positive-NAND Gates

What is the range that would be considered a logic HI? In this diagram, observe that the output stage consists of two active elements, Q3 and Q4. Let us examine the typical totem-pole output once again. If you examine a typical circuit board today you will find more use of large ICs with hundreds of pins and fewer style ICs.

Open-Collector Output Figure 6. Problem 11 – Monostable Multivibrator The circuit shows one-half of a 74LS dual “one-shot” monostable multivibrator being used to generate a pulse of adjustable width. An unconnected input is said to be floating. This configuration with Q4 stacked on top of Q3 is referred to as a totem-pole output.

That is, from Ohm’s Law one talks about 1 volt across 1 ohm produces 1 ampere. Problem 3 – Input Currents The inputs of logic gates present loads within a circuit.

In other words, when Q3 is closed, Q4 is open. These loads are characterized as input currents and will differ depending on whether the input logic level is LO or HI. In order for outputs to present a logic LO they have to have current-sinking capabilities. Also shown in Figure 6.

## (PDF) 74AS00 Datasheet download

The tri-state bus driver has an enable input G. All datsheet and debugging is conducted on the computer before the chip is created. In contrast with a normal totem-pole output, it cannot be the source of current and therefore cannot present a logic-HI on its own. The final chip may either be burned on the spot using a programmable logic array PLA or may be produced in higher volumes by the IC manufacturer.

From the measurements taken determine the propagation delay of a typical gate. Using a very high frequency clock input 74qs00 the propagation delay of a typical 74xx or 74LSxx TTL gate. What is the minimum and maximum values of R and C? A good analogy to this is the pull-cord on a city bus which one pulls when requesting the driver to stop.

Two important factors in the consideration of each logic family are speed and power consumption.